The present invention relates to a single polysilicon level flash EEPROM cell, and to a manufacturing process for obtaining the same.
It is known that a flash EEPROM cell is a memory cell that can be electrically programmed and electrically erased. The cell comprises source and drain electrodes, a floating gate and a control gate. Programming of the memory cell involves injection of hot electrons from the drain electrode into the floating gate, where the electrons get trapped. Erasure is achieved by means of Fowler-Nordheim tunneling of electrons from the floating gate normally to the source electrode.
Conventional flash EEPROM cells are stacked-gate devices wherein the floating gate is formed of a first level of polysilicon isolated from the semiconductor substrate by means of an oxide layer, and the control gate is formed of a second level of polysilicon isolated from the floating gate by means of a dielectric layer.
In order to fabricate flash EEPROM devices, manufacturing processes providing for two levels of polysilicon are necessary, and the number of additional masks with respect to a conventional CMOS manufacturing process is rather high.
Consequently, conventional flash EEPROM devices are rather costly.
In view of the state of the art described, it is an object of the present invention to provide a flash EEPROM memory cell which is simpler and cheaper to be fabricated that conventional flash EEPROM cells.
According to the present invention, such object is achieved by means of a flash EEPROM memory cell comprising source and drain regions defining a channel region therebetween, a floating gate and a control gate, characterized in that said source and drain regions are first and second doped semiconductor regions of a first conductivity type formed in a first active area region of a semiconductor material layer of a second conductivity type, said control gate comprises a third doped semiconductor region of the first conductivity type formed in a second active area region of the semiconductor material layer, and the floating gate comprises a polysilicon strip insulatively disposed over said channel region and insulatively extending over said third doped semiconductor region.
The flash EEPROM cell of the present invention can be fabricated by means of a process providing for:
forming in a semiconductor layer of a first conductivity type a first and a second active area regions delimited by field oxide layer portions;
forming in said first active area region first and second doped semiconductor regions of a second conductivity type constituting a source and a drain of the cell and defining therebetween a channel region, and forming in the second active area region a third doped semiconductor region of the second conductivity type constituting a control gate of the cell;
insulatively forming over the channel region and over the third doped region a strip of polysilicon constituting a floating gate of the cell.
The flash EEPROM memory cell according to the present invention has a single polysilicon level; thanks to this, it is simpler and cheaper to be fabricated. In fact, it can be fabricated by means of conventional CMOS processes with the addition of only a few dedicated masks. For example, in CMOS processes providing for the integration of capacitors, the source and drain regions and the control gate region of the cell can be formed by means of the same implant used to form the capacitors. The formation of the floating gate of the cell can be accomplished simultaneously with the formation of gates of MOS transistors: if the thickness of the oxide layer which insulates the gate of the MOS transistors from their channels is sufficiently low, said oxide layer can also form the tunnel oxide layer for the flash EEPROM cell, otherwise a single additional mask is necessary to form the tunnel oxide layer for the cell. In alternative, the formation of the control gate region of the cell can be obtained using the same implant step provided in all CMOS processes for the formation of well regions in the substrate for the integration of MOS transistors, and the formation of the source and drain regions of the cell can be achieved by means of a dedicated masked implant; in this case, even if a further additional mask is necessary, the performances of the memory cell can be improved. Even better performances can be achieved by forming the control gate using the capacitor implant, and forming the source and drain regions of the cell by means of said dedicated implant: since the capacitor implant has generally an implant dose higher than that of the implant for the formation of the well regions, the capacitive coupling between the floating gate and the control gate is higher, and the area of the cell can be reduced.
The features of the present invention will be made more evident by the following detailed description of some embodiments thereof, described as non-limiting examples in the annexed drawings.